The first flip-flop (the one with the Q 0 output), has a positive-edge triggered clock input, so it toggles with each rising edge of the clock signal. This circuit would yield the following output waveforms, when “clocked” by a repetitive source of pulses from an oscillator: If we used flip-flops with negative-edge triggering (bubble symbols on the clock inputs), we could simply connect the clock input of each flip-flop to the Q output of the flip-flop before it, so that when the bit before it changes from a 1 to a 0, the “falling edge” of that signal would “clock” the next flip-flop to toggle the next bit: The Q outputs of each flip-flop will serve as the respective binary bits of the final, four-bit count:
Starting with four J-K flip-flops connected in such a way to always be in the “toggle” mode, we need to determine how to connect the clock inputs in such a way so that each succeeding bit toggles when the bit before it transitions from 1 to 0. Small arrows indicate those points in the sequence where a bit toggles, the head of the arrow pointing to the previous bit transitioning from a “high” (1) state to a “low” (0) state: Note that each bit in this four-bit sequence toggles when the bit before it (the bit having a lesser significance, or place-weight), toggles in a particular direction: from 1 to 0. Examine the following binary count sequence, paying attention to patterns preceding the “toggling” of a bit between 0 and 1: The main problem facing us is to determine how to connect these flip-flops together so that they toggle at the right times to produce the proper binary sequence. Since we know that binary count sequences follow a pattern of octave (factor of 2) frequency division, and that J-K flip-flop multivibrators set up for the “toggle” mode are capable of performing this type of frequency division, we can envision a circuit made up of several J-K flip-flops, cascaded to produce four bits of output.
Since it would be desirable to have a circuit that could count forward and not just backward, it would be worthwhile to examine a forward count sequence again and look for more patterns that might indicate how to build such a circuit. In the previous section, we saw a circuit using one J-K flip-flop that counted backward in a two-bit binary sequence, from 11 to 10 to 01 to 00. This work is licensed under a Creative Commons Attribution-NonCommercial-ShareAlike 3.0 License. Electronics_Technology/Book%3A_Electric_Circuits_IV_-_Digital_Circuitry_(Kuphaldt)/11%3A_Sequential_Circuits
If we wanted to design a digital circuit to “count” in four-bit binary, all we would have to do is design a series of frequency divider circuits, each circuit dividing the frequency of a square-wave pulse by a factor of 2: Sixteen-step count sequence: at the transition between 7 (0111) and 8 (1000). The most significant bit (MSB) only toggles once during the entire Note how the least significant bit (LSB) toggles between 0 and 1 for every step in the count sequence, while each succeeding bit toggles at one-half the frequency of the one before it. If we examine a four-bit binary count sequence from 0000 to 1111, a definite pattern will be evident in the “oscillations” of the bits between 0 and 1: